Sundance-spas ST201 Manual de usuario

Busca en linea o descarga Manual de usuario para Hardware Sundance-spas ST201. Sundance Spas ST201 User Manual Manual de usuario

  • Descarga
  • Añadir a mis manuales
  • Imprimir
  • Pagina
    / 145
  • Tabla de contenidos
  • MARCADORES
  • Valorado. / 5. Basado en revisión del cliente
Vista de pagina 0
ST201
Fast Ethernet MAC
See Sundance Technologys website at www.sundanceti.com for the latest information.
Sundance Technology
Publication: 2 Rev: A
Date: November 1998
PRELIMINARY draft 2
FEATURES
Single chip 10/100BASE, half or full duplex
Ethernet Media Access Controller
IEEE 802.3u compliant MII
IEEE 802.3x full duplex flow control
PCI Bus master scatter/gather DMA on any
byte boundary
On-chip transmit and receive FIFO buffers
On-chip LED drivers
Power management capabilities for ACPI
1.0 compliant systems
WakeOnLAN support
Management statistics gathering
IP multicast receive and filter support using
64 bit hash table
Receive early interrupt
Transmit polling
Auto pad insertion for short packets
Programmable minimum Inter Packet Gap
Programmable transmit and receive FIFO
watermarks
On-chip crystal oscillator
3.3V CMOS with 5V tolerant I/O
0.35µm technology
128-pin PQFP
GENERAL DESCRIPTION
The ST201 is a single-chip, full duplex, 10/
100Mbps Ethernet MAC incorporating a 32-bit PCI
including bus master support. The ST201 is
designed for use in a variety of applications rang-
ing from workstation NICs, networking equipment
such as switches or routers, and other systems uti-
lizing a PCI bus which require network connectivity
to an Ethernet or Fast Ethernet LAN.
The ST201 includes a PCI bus interface unit, IEEE
802.3 compliant MAC, transmit and receive FIFO
buffers, IEEE 802.3u compliant MII, serial Electri-
cally EEPROM interface, expansion ROM inter-
face, and LED drivers.
The ST201 implements a rich set of control and
status registers. Accessible via the PCI interface,
these registers provide a host system visibility into
the features and operating state of the ST201. Net-
work management statistics are also recorded, and
host access to registers of the PHY device are
facilitated through the ST201s PCI interface.
The ST201 supports several features for use in
Green PCsor systems where control over system
power consumption is desired. The ST201 sup-
ports several power down states, and the ability to
issue a system wake eventvia reception of
unique, user defined Ethernet frames. In addition,
the ST201 can assert a wake event in response to
changes in the Ethernet link status.
Vista de pagina 0
1 2 3 4 5 6 ... 144 145

Indice de contenidos

Pagina 1 - Sundance Technology

ST201Fast Ethernet MACSee Sundance Technology’s website at www.sundanceti.com for the latest information.Sundance TechnologyPublication: 2 Rev: ADate:

Pagina 2

10Sundance Technology ST201 PRELIMINARY draft 2ACRONYMS AND GLOSSARYLAN Local Area NetworkMAC Media Access Control Layer, or adevice implementing the

Pagina 3 - ORDERING INFORMATION

100Sundance Technology ST201 PRELIMINARY draft 2OCTETSRECEIVEDOKClass...I/O Registers, StatisticsBase Address ...IoBaseAddress reg

Pagina 4 - PIN DIAGRAM

101Sundance Technology ST201 PRELIMINARY draft 2OCTETSTRANSMITTEDOKClass...I/O Registers, StatisticsBase Address ...IoBaseAddress

Pagina 5 - PIN DESIGNATIONS

102Sundance Technology ST201 PRELIMINARY draft 2SINGLECOLLISIONFRAMESClass...I/O Registers, StatisticsBase Address ...IoBaseAddres

Pagina 6 - PIN DESCRIPTIONS

103Sundance Technology ST201 PRELIMINARY draft 2PCI CONFIGURATION REGISTERSPCI based systems use a slot-specific block of configuration registers to p

Pagina 7

104Sundance Technology ST201 PRELIMINARY draft 2byte 3 byte 2 byte 1 byte 0 OffsetFIGURE 12: ST201 PCI Register LayoutReserved PowerMgmtCtrl 0x54Reser

Pagina 8

105Sundance Technology ST201 PRELIMINARY draft 2CACHELINESIZEClass...PCI Configuration Registers, ConfigurationBase Address ...PCI

Pagina 9

106Sundance Technology ST201 PRELIMINARY draft 2CAPPTRClass...PCI Configuration Registers, ConfigurationBase Address ...PCI device

Pagina 10 - FUNCTIONAL DESCRIPTION

107Sundance Technology ST201 PRELIMINARY draft 2CLASSCODEClass...PCI Configuration Registers, ConfigurationBase Address ...PCI dev

Pagina 11

108Sundance Technology ST201 PRELIMINARY draft 2CONFIGCOMMANDClass...PCI Configuration Registers, ConfigurationBase Address ...PCI

Pagina 12

109Sundance Technology ST201 PRELIMINARY draft 2CONFIGSTATUSClass...PCI Configuration Registers, ConfigurationBase Address ...PCI

Pagina 13

11Sundance Technology ST201 PRELIMINARY draft 2PCI BUS INTERFACEThe PCI Bus Interface (PBI) implements the proce-dures and algorithms needed to link t

Pagina 14

110Sundance Technology ST201 PRELIMINARY draft 2DEVICEIDClass...PCI Configuration Registers, ConfigurationBase Address ...PCI devi

Pagina 15

111Sundance Technology ST201 PRELIMINARY draft 2EXPROMBASEADDRESSClass...PCI Configuration Registers, ConfigurationBase Address ...

Pagina 16

112Sundance Technology ST201 PRELIMINARY draft 2HEADERTYPEClass...PCI Configuration Registers, ConfigurationBase Address ...PCI de

Pagina 17

113Sundance Technology ST201 PRELIMINARY draft 2INTERRUPTLINEClass...PCI Configuration Registers, ConfigurationBase Address ...PCI

Pagina 18

114Sundance Technology ST201 PRELIMINARY draft 2INTERRUPTPINClass...PCI Configuration Registers, ConfigurationBase Address ...PCI

Pagina 19 - PCI BUS MASTER OPERATION

115Sundance Technology ST201 PRELIMINARY draft 2IOBASEADDRESSClass...PCI Configuration Registers, ConfigurationBase Address ...PCI

Pagina 20 - POWER MANAGEMENT

116Sundance Technology ST201 PRELIMINARY draft 2LATENCYTIMERClass...PCI Configuration Registers, ConfigurationBase Address ...PCI

Pagina 21

117Sundance Technology ST201 PRELIMINARY draft 2MAXLATClass...PCI Configuration Registers, ConfigurationBase Address ...PCI device

Pagina 22 - INFORMATION

118Sundance Technology ST201 PRELIMINARY draft 2MEMBASEADDRESSClass...PCI Configuration Registers, ConfigurationBase Address ...PC

Pagina 23

119Sundance Technology ST201 PRELIMINARY draft 2MINGNTClass...PCI Configuration Registers, ConfigurationBase Address ...PCI device

Pagina 24

12Sundance Technology ST201 PRELIMINARY draft 2EXPANSION ROM INTERFACEThe ST201 provides support for an optional Expan-sion ROM. The ST201 supports th

Pagina 25

120Sundance Technology ST201 PRELIMINARY draft 2REVISIONIDClass...PCI Configuration Registers, ConfigurationBase Address ...PCI de

Pagina 26

121Sundance Technology ST201 PRELIMINARY draft 2SUBSYSTEMIDClass...PCI Configuration Registers, ConfigurationBase Address ...PCI d

Pagina 27

122Sundance Technology ST201 PRELIMINARY draft 2SUBSYSTEMVENDORIDClass...PCI Configuration Registers, ConfigurationBase Address ...

Pagina 28

123Sundance Technology ST201 PRELIMINARY draft 2VENDORIDClass...PCI Configuration Registers, ConfigurationBase Address ...PCI devi

Pagina 29

124Sundance Technology ST201 PRELIMINARY draft 2CAPIDClass...PCI Configuration Registers, Power ManagementBase Address ...PCI devi

Pagina 30

125Sundance Technology ST201 PRELIMINARY draft 2NEXTITEMPTRClass...PCI Configuration Registers, Power ManagementBase Address ...PC

Pagina 31

126Sundance Technology ST201 PRELIMINARY draft 2POWERMGMTCAPClass...PCI Configuration Registers, Power ManagementBase Address ...P

Pagina 32

127Sundance Technology ST201 PRELIMINARY draft 2POWERMGMTCTRLClass...PCI Configuration Registers, Power ManagementBase Address ...

Pagina 33

128Sundance Technology ST201 PRELIMINARY draft 2EEPROM DATA FORMATFigure 13 summarizes the layout of the EEPROM.byte 0 OffsetFIGURE 13: EEPROM Data La

Pagina 34

129Sundance Technology ST201 PRELIMINARY draft 2CONFIGPARMClass...EEPROM Data FormatBase Address ...0x00, address written to Eepro

Pagina 35

13Sundance Technology ST201 PRELIMINARY draft 2dress register. Setting the ReceiveBroadcast andReceiveMulticast bits in the ReceiveMode registerwill a

Pagina 36

130Sundance Technology ST201 PRELIMINARY draft 2STATIONADDRESSClass...EEPROM Data FormatBase Address ...0x00, address written to E

Pagina 37

131Sundance Technology ST201 PRELIMINARY draft 2ASICCTRLClass...EEPROM Data FormatBase Address ...0x00, address written to EepromC

Pagina 38

132Sundance Technology ST201 PRELIMINARY draft 214..8 Reserved Reserved for future use. Should be set to 0.15 ResetPolarity Setting this read/write bi

Pagina 39

133Sundance Technology ST201 PRELIMINARY draft 2SUBSYSTEMVENDORIDClass...EEPROM Data FormatBase Address ...0x00, address written t

Pagina 40

134Sundance Technology ST201 PRELIMINARY draft 2SUBSYSTEMIDClass...EEPROM Data FormatBase Address ...0x00, address written toEepro

Pagina 41

135Sundance Technology ST201 PRELIMINARY draft 2ABSOLUTE MAXIMUM RATINGSStorage Temperature ...-65ºC to +150ºCAmbient Temperature...

Pagina 42

136Sundance Technology ST201 PRELIMINARY draft 2DC CHARACTERISTICSDC characteristics are defined over commercial operating ranges unless specified oth

Pagina 43

137Sundance Technology ST201 PRELIMINARY draft 2PIN TYPE OD6 (OPEN DRAIN OUTPUT BUFFER)VOLOutput low voltage IOL = 6mA 0.4 VIOZOutput leakage current

Pagina 44

138Sundance Technology ST201 PRELIMINARY draft 2MISC INTERFACEITU/OT4 GPIO0, GPIO1OT4 RSTOUTOD8 LEDPWRN, LEDLNKN, LEDDPLXN, LEDSPDNOC4 CLK25OSCI X25I

Pagina 45

139Sundance Technology ST201 PRELIMINARY draft 2SWITCHING CHARACTERISTICSPARAMETER SYMBOLPARAMETER DESCRIPTIONTEST CONDITIONS MIN MAX UNITPCI INTERFAC

Pagina 46

14Sundance Technology ST201 PRELIMINARY draft 2TXDMA AND FRAME TRANSMISSIONThe TxDMA block transfers frame data from a hostsystem to the ST201 based o

Pagina 47

140Sundance Technology ST201 PRELIMINARY draft 2TwhEWEN write cycle high 100 - -TwlEWEN write cycle low 90 - -EEPROM INTERFACETskcEESK cycle 1us - -Ts

Pagina 48

141Sundance Technology ST201 PRELIMINARY draft 2MII INTERFACE - MANAGEMENTTccMDC cycle 400 - -TchMDC high 160 - -TclMDC low 160 - -TsuMDIO setup wrt M

Pagina 49 - The hash table is cleared

142Sundance Technology ST201 PRELIMINARY draft 2tabcST201RSTNPCICLKGNTNREQNBUSSEDtrctcltcctchtrvtrvptrvptroztsutsup2trzotsup1thdtrstoffSIGNALSANY SIGN

Pagina 50

143Sundance Technology ST201 PRELIMINARY draft 2EECSEESKEEDIEEDOD0D15A7 A0tcstskltcsktskhtpdtdostdohtcshST201FIGURE 16: EEPROM Switching Characteristi

Pagina 51

144Sundance Technology ST201 PRELIMINARY draft 2ST201trvtrhtrhtcltcctchtsuthdtcltcctchtsuthdtsuthdtrvtrvthdtcltcctchTXD[3..0]TXENTXCLKRXD[3..0]RXERRXD

Pagina 52

Copyright Sundance Technology, Inc., 1998. The information contained in this data sheet is subject to change without notice. Sun-dance Technology assu

Pagina 53

15Sundance Technology ST201 PRELIMINARY draft 2The TxDMAListPtr I/O register within the ST201contains the physical address that points to thehead o

Pagina 54

16Sundance Technology ST201 PRELIMINARY draft 2are independent of each other in general. A specialcase is when a transmit under run occurs. In thiscas

Pagina 55

17Sundance Technology ST201 PRELIMINARY draft 2received and transferred by RxDMA, a RxDMA-Complete interrupt will be generated for eachframe.The host

Pagina 56

18Sundance Technology ST201 PRELIMINARY draft 2Systems using the ST201 can be programmed togenerate an interrupt based upon the number ofbytes that ha

Pagina 57

19Sundance Technology ST201 PRELIMINARY draft 2STATISTICSThe ST201 implements 16 statistics counters ofvarious widths. Each statistic implemented com

Pagina 58

2Sundance Technology ST201 PRELIMINARY draft 2BLOCK DIAGRAMPHYLNKNRSTNPCICLKGNTNIDSELINTANWAKEREQNAD[31..0]CBEN[3:0]PARFRAMENIRDYNTRDYNDEVSELNSTOPNPER

Pagina 59

20Sundance Technology ST201 PRELIMINARY draft 2disable the use of MWI and MRL. MWIDisable andMRLDisable are cleared by default, enabling MWIand MRL.Th

Pagina 60

21Sundance Technology ST201 PRELIMINARY draft 2D1, D2, or D3. When the ST201 detects a WakePacket, it signals a wake event on PMEN (if PMENassertion i

Pagina 61

22Sundance Technology ST201 PRELIMINARY draft 2network via transmission of a special frame. Oncethe ST201 has been placed in Magic Packet modeand put

Pagina 62

23Sundance Technology ST201 PRELIMINARY draft 23. Set MgmtClk4. Write the desired data bit to MgmtData5. Wait a minimum of 200 nsTo perform a Z cycle

Pagina 63

24Sundance Technology ST201 PRELIMINARY draft 28. Verify EepromBusy is false.9. Issue WriteRegister command(opcode = 01 aaaa aaaa)Step 4 through 8 may

Pagina 64

25Sundance Technology ST201 PRELIMINARY draft 2tion of the “first TFD” in the TxDMAList. Restore the TxDMANextPtr of the “first TFD”, and restart this

Pagina 65

26Sundance Technology ST201 PRELIMINARY draft 2host system then returns to the operating sys-tem an indication of readiness to be powered down (making

Pagina 66

27Sundance Technology ST201 PRELIMINARY draft 2REGISTERS AND DATA STRUCTURESDMA DATA STRUCTURESA TFD is used to move data, which is to be transmitted

Pagina 67

28Sundance Technology ST201 PRELIMINARY draft 2TXDMAFRAGADDRClass...DMA Data Structures, TFDBase Address ...Start of TFDAddress Of

Pagina 68

29Sundance Technology ST201 PRELIMINARY draft 2TXDMAFRAGLENClass...DMA Data Structures, TFDBase Address ...Start of TFDAddress Off

Pagina 69

3Sundance Technology ST201 PRELIMINARY draft 2ORDERING INFORMATIONK CTEMPERATURE RANGEPACKAGE TYPEDEVICE NUMBER/DESCRIPTIONST201C=Commercial (0 to +70

Pagina 70

30Sundance Technology ST201 PRELIMINARY draft 2TXDMANEXTPTRClass...DMA Data Structures, TFDBase Address ...Start of TFDAddress Off

Pagina 71

31Sundance Technology ST201 PRELIMINARY draft 2TXFRAMECONTROLClass...DMA Data Structures, TFDBase Address ...Start of TFDAddress O

Pagina 72

32Sundance Technology ST201 PRELIMINARY draft 2RXDMANEXTPTRClass...DMA Data Structures, RFDBase Address ...Start of RFDAddress Off

Pagina 73

33Sundance Technology ST201 PRELIMINARY draft 2RXFRAMESTATUSClass...DMA Data Structures, RFDBase Address ...Start of RFDAddress Of

Pagina 74

34Sundance Technology ST201 PRELIMINARY draft 222..21 Reserved Reserved for future use. Should be set to 0.23 DribbleBits Indicates that the frame had

Pagina 75

35Sundance Technology ST201 PRELIMINARY draft 2RXDMAFRAGADDRClass...DMA Data Structures, RFDBase Address ...Start of RFDAddress Of

Pagina 76

36Sundance Technology ST201 PRELIMINARY draft 2RXDMAFRAGLENClass...DMA Data Structures, RFDBase Address ...Start of RFDAddress Off

Pagina 77

37Sundance Technology ST201 PRELIMINARY draft 2WAKE EVENT DATA STRUCTURESThe first Wake Event Data Structure is the Pseudo Packet. A Pseudo Packet is

Pagina 78

38Sundance Technology ST201 PRELIMINARY draft 2PSEUDOPATTERNClass...Wake Event Data Structures, Pseudo PacketBase Address ...Start

Pagina 79

39Sundance Technology ST201 PRELIMINARY draft 2TERMINATORClass...Wake Event Data Structures, Pseudo PacketBase Address ...Start of

Pagina 80

4Sundance Technology ST201 PRELIMINARY draft 2PIN DIAGRAM

Pagina 81

40Sundance Technology ST201 PRELIMINARY draft 2PSEUDOCRCClass...Wake Event Data Structures, Pseudo PacketBase Address ...Start of

Pagina 82

41Sundance Technology ST201 PRELIMINARY draft 2MAGICSYNCSTREAMClass...Wake Event Data Structures, Magic PacketBase Address ...Star

Pagina 83

42Sundance Technology ST201 PRELIMINARY draft 2MAGICSEQUENCEClass...Wake Event Data Structures, Magic PacketBase Address ...Start

Pagina 84

43Sundance Technology ST201 PRELIMINARY draft 2I/O REGISTERSThe host interacts with the ST201 mainly through slave registers, which occupy 128 bytes i

Pagina 85

44Sundance Technology ST201 PRELIMINARY draft 2McstFramesRcvdOk McstFramesXmtdOk BcstFramesRcvdOk BcstFramesXmtdOk 0x7cFramesAbortXSColls FramesWEXDef

Pagina 86

45Sundance Technology ST201 PRELIMINARY draft 2ASICCTRLClass...I/O Registers, Control and StatusBase Address ...IoBaseAddress regi

Pagina 87

46Sundance Technology ST201 PRELIMINARY draft 210..8 ForcedConfig These bits are used to place the ST201 into Forced Configuration mode. The bit value

Pagina 88

47Sundance Technology ST201 PRELIMINARY draft 219 DMA When set, together with GlobalReset, RxReset, or TxReset bits, will reset RxDMA and TxDMA Logic,

Pagina 89

48Sundance Technology ST201 PRELIMINARY draft 2DEBUGCTRLClass...I/O Registers, Control and StatusBase Address ...IoBaseAddress reg

Pagina 90

49Sundance Technology ST201 PRELIMINARY draft 2HASHTABLEClass...I/O Registers, Control and StatusBase Address ...IoBaseAddress reg

Pagina 91

5Sundance Technology ST201 PRELIMINARY draft 2PIN DESIGNATIONSPIN NO.PIN NAMEPIN NO.PIN NAMEPIN NO.PIN NAMEPIN NO.PIN NAME1 VCC (5V) 33 AD9 65 EA2 97

Pagina 92

50Sundance Technology ST201 PRELIMINARY draft 2MACCTRLClass...I/O Registers, Control and StatusBase Address ...IoBaseAddress regis

Pagina 93

51Sundance Technology ST201 PRELIMINARY draft 29 RcvFCS This bit is set by the host if it is desired for the receive frame’s FCS tobe passed to the ho

Pagina 94

52Sundance Technology ST201 PRELIMINARY draft 2The loopback modes available to a host system when using the ST201 are shown in Table 3.External loopba

Pagina 95

53Sundance Technology ST201 PRELIMINARY draft 2MAXFRAMESIZEClass...I/O Registers, Control and StatusBase Address ...IoBaseAddress

Pagina 96

54Sundance Technology ST201 PRELIMINARY draft 2RECEIVEMODEClass...I/O Registers, Control and StatusBase Address ...IoBaseAddress r

Pagina 97

55Sundance Technology ST201 PRELIMINARY draft 2STATIONADDRESSClass...I/O Registers, Control and StatusBase Address ...IoBaseAddres

Pagina 98

56Sundance Technology ST201 PRELIMINARY draft 2TXFRAMEIDClass...I/O Registers, Control and StatusBase Address ...IoBaseAddress reg

Pagina 99

57Sundance Technology ST201 PRELIMINARY draft 2TXSTATUSClass...I/O Registers, Control and StatusBase Address ...IoBaseAddress regi

Pagina 100

58Sundance Technology ST201 PRELIMINARY draft 2WAKEEVENTClass...I/O Registers, Control and StatusBase Address ...IoBaseAddress reg

Pagina 101

59Sundance Technology ST201 PRELIMINARY draft 2FIFOCTRLClass...I/O Registers, FIFO ControlBase Address ...IoBaseAddress register v

Pagina 102

6Sundance Technology ST201 PRELIMINARY draft 2PIN DESCRIPTIONSPIN NAME PIN TYPE PIN DESCRIPTIONPCI INTERFACERSTN INPUT Reset, asserted LOW. RSTN will

Pagina 103

60Sundance Technology ST201 PRELIMINARY draft 2RXEARLYTHRESHClass...I/O Registers, FIFO ControlBase Address ...IoBaseAddress regis

Pagina 104

61Sundance Technology ST201 PRELIMINARY draft 2TXRELEASETHRESHClass...I/O Registers, FIFO ControlBase Address ...IoBaseAddress reg

Pagina 105

62Sundance Technology ST201 PRELIMINARY draft 2TXSTARTTHRESHClass...I/O Registers, FIFO ControlBase Address ...IoBaseAddress regis

Pagina 106

63Sundance Technology ST201 PRELIMINARY draft 2COUNTDOWNClass...I/O Registers, InterruptBase Address ...IoBaseAddress register val

Pagina 107

64Sundance Technology ST201 PRELIMINARY draft 2INTENABLEClass...I/O Registers, InterruptBase Address ...IoBaseAddress register val

Pagina 108

65Sundance Technology ST201 PRELIMINARY draft 2INTSTATUSClass...I/O Registers, InterruptBase Address ...IoBaseAddress register val

Pagina 109

66Sundance Technology ST201 PRELIMINARY draft 29 TxDMAComplete This bit indicates that a frame TxDMA has completed, and the TFD inquestion had the TxD

Pagina 110

67Sundance Technology ST201 PRELIMINARY draft 2INTSTATUSACKClass...I/O Registers, InterruptBase Address ...IoBaseAddress register

Pagina 111

68Sundance Technology ST201 PRELIMINARY draft 29 TxDMAComplete This bit indicates that a frame TxDMA has completed, and the TFD inquestion had the TxD

Pagina 112

69Sundance Technology ST201 PRELIMINARY draft 2DMACTRLClass...I/O Registers, DMABase Address ...IoBaseAddress register valueAddres

Pagina 113

7Sundance Technology ST201 PRELIMINARY draft 2TRDYN IN/OUT Target Ready, asserted LOW. A bus target asserts TRDYN to indicate valid read data phases,

Pagina 114

70Sundance Technology ST201 PRELIMINARY draft 215 DMAHaltBusy This read-only bit indicates that a DMA Halt operation (TxDMAHalt orRxDMAHalt) is in pro

Pagina 115

71Sundance Technology ST201 PRELIMINARY draft 231 MasterAbort This read-only bit is set when the ST201 experiences a master abortsequence when operati

Pagina 116

72Sundance Technology ST201 PRELIMINARY draft 2RXDMABURSTTHRESHClass...I/O Registers, DMABase Address ...IoBaseAddress register va

Pagina 117

73Sundance Technology ST201 PRELIMINARY draft 2RXDMALISTPTRClass...I/O Registers, DMABase Address ...IoBaseAddress register valueA

Pagina 118

74Sundance Technology ST201 PRELIMINARY draft 2RXDMASTATUSClass...I/O Registers, DMABase Address ...IoBaseAddress register valueAd

Pagina 119

75Sundance Technology ST201 PRELIMINARY draft 220 RxOversizedFrame Indicates the frame size was equal to or greater than the value set inthe MaxFrameS

Pagina 120

76Sundance Technology ST201 PRELIMINARY draft 2RXDMAPOLLPERIODClass...I/O Registers, DMABase Address ...IoBaseAddress register val

Pagina 121

77Sundance Technology ST201 PRELIMINARY draft 2RXDMAURGENTTHRESHClass...I/O Registers, DMABase Address ...IoBaseAddress register v

Pagina 122

78Sundance Technology ST201 PRELIMINARY draft 2TXDMABURSTTHRESHClass...I/O Registers, DMABase Address ...IoBaseAddress register va

Pagina 123

79Sundance Technology ST201 PRELIMINARY draft 2TXDMALISTPTRClass...I/O Registers, DMABase Address ...IoBaseAddress register valueA

Pagina 124

8Sundance Technology ST201 PRELIMINARY draft 2COL INPUT Collision. COL is asserted by the PHY to a signal collision condition is detected on the physi

Pagina 125

80Sundance Technology ST201 PRELIMINARY draft 2TXDMAPOLLPERIODClass...I/O Registers, DMABase Address ...IoBaseAddress register val

Pagina 126

81Sundance Technology ST201 PRELIMINARY draft 2TXDMAURGENTTHRESHClass...I/O Registers, DMABase Address ...IoBaseAddress register v

Pagina 127

82Sundance Technology ST201 PRELIMINARY draft 2EEPROMCTRLClass...I/O Registers, External Interface ControlBase Address ...IoBaseAd

Pagina 128

83Sundance Technology ST201 PRELIMINARY draft 2EEPROMDATAClass...I/O Registers, External Interface ControlBase Address ...IoBaseAd

Pagina 129

84Sundance Technology ST201 PRELIMINARY draft 2EXPROMADDRClass...I/O Registers, External Interface ControlBase Address ...IoBaseAd

Pagina 130

85Sundance Technology ST201 PRELIMINARY draft 2EXPROMDATAClass...I/O Registers, External Interface ControlBase Address ...IoBaseAd

Pagina 131

86Sundance Technology ST201 PRELIMINARY draft 2PHYCTRLClass...I/O Registers, External Interface ControlBase Address ...IoBaseAddre

Pagina 132 - BIT BIT NAME BIT DESCRIPTION

87Sundance Technology ST201 PRELIMINARY draft 2STATISTICSReading a statistic register will clear it. The statistics gathering must be enabled by setti

Pagina 133

88Sundance Technology ST201 PRELIMINARY draft 2BROADCASTFRAMESTRANSMITTEDOKClass...I/O Registers, StatisticsBase Address ...IoBase

Pagina 134

89Sundance Technology ST201 PRELIMINARY draft 2CARRIERSENSEERRORSClass...I/O Registers, StatisticsBase Address ...IoBaseAddress re

Pagina 135 - OPERATING RANGES

9Sundance Technology ST201 PRELIMINARY draft 2LEDPWRN OUTPUT Power Status LED. (This pin is shared with EA9). The operation of this pin varies based o

Pagina 136 - DC CHARACTERISTICS

90Sundance Technology ST201 PRELIMINARY draft 2FRAMESABORTEDDUETOXSCOLLSClass...I/O Registers, StatisticsBase Address ...IoBaseAdd

Pagina 137

91Sundance Technology ST201 PRELIMINARY draft 2FRAMESLOSTRXERRORSClass...I/O Registers, StatisticsBase Address ...IoBaseAddress re

Pagina 138

92Sundance Technology ST201 PRELIMINARY draft 2FRAMESRECEIVEDOKClass...I/O Registers, StatisticsBase Address ...IoBaseAddress regi

Pagina 139 - SWITCHING CHARACTERISTICS

93Sundance Technology ST201 PRELIMINARY draft 2FRAMESTRANSMITTEDOKClass...I/O Registers, StatisticsBase Address ...IoBaseAddress r

Pagina 140

94Sundance Technology ST201 PRELIMINARY draft 2FRAMESWITHDEFERREDXMISSIONClass...I/O Registers, StatisticsBase Address ...IoBaseAd

Pagina 141

95Sundance Technology ST201 PRELIMINARY draft 2FRAMESWITHEXCESSIVEDEFERALClass...I/O Registers, StatisticsBase Address ...IoBaseAd

Pagina 142

96Sundance Technology ST201 PRELIMINARY draft 2LATECOLLISIONSClass...I/O Registers, StatisticsBase Address ...IoBaseAddress regist

Pagina 143

97Sundance Technology ST201 PRELIMINARY draft 2MULTICASTFRAMESRECEIVEDOKClass...I/O Registers, StatisticsBase Address ...IoBaseAdd

Pagina 144

98Sundance Technology ST201 PRELIMINARY draft 2MULTICASTFRAMESTRANSMITTEDOKClass...I/O Registers, StatisticsBase Address ...IoBase

Pagina 145 - PHYSICAL DIMENSIONS

99Sundance Technology ST201 PRELIMINARY draft 2MULTIPLECOLLISIONFRAMESClass......I/O Registers, StatisticsBase Address ...IoBaseAddre

Comentarios a estos manuales

Sin comentarios